> Home > Schedule & Program > Technical Program

TECHNICAL Program

A PDF version of the tentative Technical Program is available here.

A PDF version of the tentative Technical Program is available here.

Technical Program At-A-Glance

Mon, May 14

Tue, May 15

Wed, May 16

Thu, May 17

08:30 Opening 3 Lateral Devices: Reliability 9 GaN Power Devices - 2 15 Novel Device Structures
08:50 Plenary 1
10:10 Coffee Break Coffee Break (10:10-10:30) Coffee Break
10:20 Coffee Break Poster Sessions (10:10-12:10):
10:30 4 Smart Power ICs 10 Low Voltage 16 IGBTs
10:40 Plenary 2 11 IC Design
12 SiC
12:10 Lunch Break Lunch Break Lunch Break Lunch Break
13:30 1 Superjunction MOS, Diodes and IGBTs 5 GaN Power Devices - 1 13 SiC Reliability and Ruggedness 17 Invited Papers
14:20 Coffee Break
14:40 Closing
15:10 Coffee Break Coffee Break Coffee Break
15:30 2 SiC Power MOSFETs Poster Sessions:
6 High Voltage
7 GaN
8 Packaging
14 Packaging and Enabling Technologies
17:30
17:35
18:30 Reception AdCom Dinner
(by Invitation)
Banquet TPC Dinner
(by Invitation)


Detailed Technical Program (Tentative)

Monday, May 14, 2018

Opening Remarks

08:30

John Shen, Illinois Institute of Technology, USA


Plenary 1

Chair:    John Shen, Illinois Institute of Technology, USA
Co-Chair:    K. Sheng, Zhejiang University, China

08:50 PL1-1

ISPSD: A 30 Year Journey in Advancing Power Semiconductor Technology
Ayman Shibib, Leo Lorentz, Hiromichi Ohashi

09:35 PL1-2

Silicon, GaN and SiC: There’s Room for All
Larry Spaziani, GaN Systems Inc., Canada


10:20 Coffee Break

Plenary 2

Chair:    Wai Tung Ng, University of Toronto, Canada
Co-Chair:    Kevin Chen, Hong Kong University of Science & Technology

10:40 PL2-1

Si Wafer Technology for Power Devices: A Review and Future Directions
Norihisa Machida, SUMCO, Japan

11:25 PL2-2

The Future of Power Semiconductors: an EU Perspecitve
Bert De Colvenaer, ECSEL, Belgium


12:10 Lunch Break

S1      Superjunction MOS, Diodes and IGBTs

Chair:    Young Chul Choi, ON Semiconductor, Korea
Co-Chair:    Marina Antoniou, University of Cambridge, UK

13:30 1-1

IGBT with Superior Long-Term Switching Behavior by Asymmetric Trench Oxide
Christian Sandow, Philip Brandt, Hans-Peter Felsl, Franz-Josef Niedernostheide, Frank Pfirsch, Francisco Santos, Hans-Joachim Schulze, André Stegner, Frank Umbach, Wolfgang Wagner, Infineon Technologies AG, Germany

13:55 1-2

6.5 kV Field Shielded Anode (FSA) Diode Concept with 150°C Maximum Operational Temperature Capability
Boni Boksteen, Charalampos Papadopoulos, Daniel Prindle, Arnost Kopta, Chiara Corvasce, ABB Semiconductors, Switzerland

14:20 1-3

Low Noise Superjunction MOSFET with Integrated Snubber Structure
Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Masataka Tsuji, Masaru Izumisawa, Wataru Saito, Toshiba Electronic Devices and Storage Corp., Japan

14:45 1-4

Breakthrough of Drain Current Capability and on-Resistance Limits by Gate- Connected Superjunction MOSFET
Wataru Saito, Toshiba Electric Devices & Storage Corp., Japan


15:10 Coffee Break

S2      SiC Power MOSFETs

Chair:    Peter Losee, General Electric, USA
Co-Chair:    Andrei Petru Mihaila, ABB, Switzerland

15:30 2-1

Investigation of Threshold Voltage Stability of SiC MOSFETs
Dethard Peters, Thomas Aichinger, Thomas Basler, Gerald Rescher, Katja Puschkarsky, Hans Reisinger, Infineon Technologies AG, Germany

15:55 2-2

Deep-P Encapsulated 4H-SiC Trench MOSFETs with Ultra Low RonQgd
Yasuhiro Ebihara, Aiko Ichimura, Shuhei Mitani, Masato Noborio, Yuichi Takeuchi, Shoji Mizuno, Toshimasa Yamamoto, Kazuhiro Tsuruta, Denso Corp., Japan

16:20 2-3

Influence of the Off-State Gate-Source Voltage on the Transient Drain Current Response in SiC MOSFETs
Christian Unger, Martin Pfost, TU Dortmund University, Germany

16:45 2-4

Reduction of RonA Retaining High Threshold Voltage in SiC DioMOS by Improved Channel Design
Atsushi Ohoka, Masao Uchida, Tsutomu Kiyosawa, Yoshihiko Kanzawa, Tetsuzo Ueda, Automotive & Industrial Systems Co., Panasonic Corp., Japan

17:10 2-5

Avalanche Ruggedness and Reverse-Bias Reliability of SiC MOSFET with Integrated Junction Barrier Controlled Schottky Rectifier
Cheng-Tyng Yen, Fu-Jen Hsu, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee, Ya-Fang Li, Kuo-Ting Chu, Hestia Power Inc., Taiwan


18:30

Reception


Tuesday, May 15, 2018

S3      Lateral Devices: Reliability

Chair:    Phil Rutter, Nexperia, UK
Co-Chair:    Jun Cai, Texas instruments, USA

08:30 3-1

Comprehensive Investigation on Mechanical Strain Induced Performance Boosts in LDMOS
Wangran Wu, Siyang Liu, Jing Zhu, Weifeng Sun, Southeast University, China

08:55 3-2

Investigation on Total-Ionizing-Dose Radiation Response for High Voltage Ultra-Thin Layer SOI LDMOS
Xin Zhou, Lingfang Zhang, Ming Qiao, Zhangyi'An Yuang, Lei Shu, Ping Luo , Zhaoji Li, Bo Zhang, University of Electronic Science and Technology of China, China

09:20 3-3

Electromigration Current Limit Relaxation for Power Device Interconnects
Jungwoo Joh, Young-Joon Park, Srikanth Krishnan, Kim Christensen, Jayhoon Chung, Texas Instruments, USA

09:45 3-4

Performance and Reliability Insights of Drain Extended FinFET Devices for High Voltage SoC Applications
Sampath Kumar Boeila, Milova Paul, Harald Gossner, Mayank Shrivastava, Indian Institute of Science, India


10:10 Coffee Break

S4      Smart Power ICs

Chair:    Nicolas Rouger, CNRS, France
Co-Chair:    Budong (Albert) You, Silergy Corp., China

10:30 4-1


10:55 4-2

High-Speed, High-Reliability GaN Power Device with Integrated Gate Driver
Gaofei Tang, Alex M.-H. Kwan, R.-Y. Su, F.-W. Yao, Y.-M. Lin, J.-L. Yu, Thomas Yang, Chan-Hong Chern, Tom Tsai, H. C. Tuan, Alexander Kalnitsky, Kevin J. Chen, Hong Kong University of Science and Technology, Hong Kong, China

11:20 4-3

A 600V High-Side Gate Drive Circuit with Ultra-Low Propagation Delay for Enhancement Mode GaN Devices
Yangyang Lu, Jing Zhu, Weifeng Sun, Yunwu Zhang, Kongsheng Hu, Zhicheng Yu, Jing Leng, Shikang Cheng, Sen Zhang, Southeast University, China

11:45 4-4

A Smart Gate Driver IC for GaN Power Transistors
Jingshu Yu, Weijia Zhang, Andrew Shorten, Rophina Li, Wai Tung Ng, University of Toronto, Canada


12:10 Lunch Break

S5      GaN Power Devices - 1

Chair:    Kevin Chen, Hong Kong University of Science and Technology, Hong Kong, China
Co-Chair:    Oliver Haeberlen, Infineon Technologies, Austria

13:30 5-1

Dynamic-Ron Control via Proton Irradiation in AlGaN/GaN Transistors
Alaleh Tajalli, Arno Stockman, Matteo Meneghini, Samir Mouhoubi, Abhishek Banerjee, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella, Enrico Zanoni, Marnix Tack, Peter Moens, Gaudenzio Meneghesso, University of Padova, Italy

13:55 5-2

Bidirectional Threshold Voltage Shift and Gate Leakage in 650 V P-GaN AlGaN/GaN HEMTs: the Role of Electron-Trapping and Hole-Injection
Yuanyuan Shi, Qi Zhou, Qian Cheng, Pengcheng Wei, Liyang Zhu, Dong Wei, Anbang Zhang, Wanjun Chen, Bo Zhang, University of Electronic Science and Technology of China, China

14:20 5-3

GaN-on-Si Lateral Power Devices with Symmetric Vertical Leakage : the Impact of Floating Substrate
Hanyuan Zhang, Shu Yang, Kuang Sheng, Zhejiang University, China

14:45 5-4

Short Circuit Robustness Analysis of New Generation Enhancement-Mode pGaN Power HEMTs
Michele Riccio, Gianpaolo Romano, Giorgia Longobardi, Luca Maresca, Giovanni Breglio, Andrea Irace, University of Naples Federico II, Italy


15:10 Coffee Break

15:30

Poster Session 6: High Voltage

15:30

Poster Session 7: GaN

15:30

Poster Session 8: Packaging


18:30

AdCom Dinner (by Invitation)


Wednesday, May 16, 2018

S9      GaN Power Devices - 2

Chair:    Peter Moens, ON Semiconductor, Belgium
Co-Chair:    Yang Liu, Sun Yat-sen University, China

08:30 9-1

1 kV/1.3 mΩ·cm2 Vertical GaN-on-GaN Schottky Barrier Diodes with High Switching Performance
Shu Yang, Shaowen Han, Rui Li, Kuang Sheng, Zhejiang University, China

08:55 9-2

Reverse-Blocking AlGaN/GaN Normally-Off Mis-HEMT with Double-Recessed Gated Schottky Drain
Jiacheng Lei, Jin Wei, Gaofei Tang, Kevin J. Chen, Hong Kong University of Science and Technology, Hong Kong, China

09:20 9-3

Recess-Free AlGaN/GaN Lateral Schottky Barrier Controlled Schottky Rectifier with Low Turn-on Voltage and High Reverse Blocking
Xuanwu Kang, Xinhua Wang, Sen Huang, Jinhan Zhang, Jie Fan, Shuo Yang, Yuankun Wang, Yingkui Zheng, Ke Wei, Xinyu Liu, IMECAS, China

09:45 9-4



10:10 Coffee Break

10:10

Poster Session 10: Low Voltage Technology

10:10

Poster Session 11: IC Design

10:10

Poster Session 12: SiC


12:10 Lunch Break

S13      SiC Reliability and Ruggedness

Chair:    Kevin Matocha, Monolith Semiconductor, USA
Co-Chair:    Yoshiyuki Yonezawa, AIST, Japan

13:30 13-1

Robustness Improvement of Short-Circuit Capability by SiC Trench-Etched Double- Diffused MOS (Ted MOS)
Naoki Tega, Kazuki Tani, Digh Hisamoto, Akio Shima, Hitachi Ltd. Japan

13:55 13-2

High-Temperature Validated SiC Power MOSFET Model for Flexible Robustness Analysis of Multi-Chip Structures
Michele Riccio, Vincenzo D'Alessandro, Gianpaolo Romano, Alberto Castellazzi, Luca Maresca, Giovanni Breglio, Andrea Irace, University of Naples Federico II, Italy

14:20 13-3

Reliability Investigation with Accelerated Body Diode Current Stress for 3.3 kV 4HSiC MOSFETs with Various Buffer Layer Thickness
Yuji Ebiike, Mitsubishi Electric Corporation, Japan

14:45 13-4

Dynamic Switching and Short Circuit Capability of 6.5kV Silicon Carbide MOSFETs
Lars Knoll, Andrei Mihaila, Enea Bianda, Lukas Kranz, Marco Bellini, Stephan Wirths, Charalampos Papadopoulus, ABB Switzerland Corporate Research, Switzerland


15:10 Coffee Break

S14      Packaging and Enabling Technologies

Chair:    Tomoyuki Miyoshi, Hitachi, Japan
Co-Chair:    Alberto Castellazzi, Nottingham University, UK

15:30 14-1

Improvement of Power Cycling Reliability of 3.3kV Full-SiC Power Modules with Sintered Copper Technology for Tj,max=175˚C
Kan Yasui, Seiichi Hayakawa, Masato Nakamura, Daisuke Kawase, Takashi Ishigaki, Kouji Sasaki, Toshihito Tabata, Masakazu Sagawa, Hiroyuki Matsushima, Toshiyuki Kobayashi, Toshiaki Morita, Hitachi Power Semiconductor Device Ltd., Japan

15:55 14-2

Enhanced Breakdown Voltage and Low Inductance of All-SiC Module
Motohito Hori, Yuichiro Hinata, Katsumi Taniguchi, Yoshinari Ikeda, Tomoyuki Yamazaki, Fuji Electric Co. Ltd., Japan

16:20 14-3

Dynamic Performance Analysis of a 3.3 kV SiC MOSFET Half-Bridge Module with Parallel Chips and Body-Diode Freewheeling
Abdallah Hussein, Bassem Mouawad, Alberto Castellazzi, University of Nottingham, UK

16:45 14-4

Power Cycling Reliability Results of GaN HEMT Devices
Jörg Franke, Tom Winkler, Josef Lutz, Chemnitz University of Technology, Germany

17:10 14-5

Individual Device Active Cooling for Enhanced System-Level Power Density and More Uniform Temperature Distribution
Yuqi Zeng, Abdallah Hussein, Alberto Castellazzi, University of Nottingham, UK


18:30

Banquet


Thursday, May 17, 2018

S15      Novel Device Structures

Chair:    Dev Alok Girdhar, Intersil, USA
Co-Chair:   

08:30 15-1

Non-Full Depletion Mode of the Lateral Superjunction and its Experimental Realization in the SOI Devices
Wentong Zhang, Song Pu, Chunlan Lai, Li Ye, Shikang Cheng, Sen Zhang, Boyong He, Zhuo Wang, Xiaorong Luo, Zhaoji Li, Ming Qiao, Bo Zhang, University of Electronic Science and Technology of China, China

08:55 15-2

Cathode Short Structure to Enhance the Robustness of Bidirectional Power MOSFETs
Tanuj Saxena, Vishnu Khemka, Moaniss Zitouni, Raghu Gupta, Ganming Qin, Philippe Dupuy, Mark Gibson, NXP Semiconductor Inc., USA

09:20 15-3

40V to 100V NLDMOS Built on Thin Box SOI with High Energy Capability, State of the Art Rdson/BVdss and Robust Performance
Hao Yang, Martin Pfost, Poh Ching Sim, Madelyn Liew, Alexander Hoelke, Uwe Eckoldt, X-FAB Semiconductor Foundries AG, Germany

09:45 15-4

Novel Integration Techniques of “Recessed” High Voltage Field-Drift MOSFET with HK/MG RMG Technology
Chang Po Hsiung, Ping Hung Chiang, Shih Chieh Pu, Chia Ling Wang, Chia Wen Lu, Kuan Liang Liu, Kai Kuen Chang, Ching Chung Yang, Nien Chung Lee, Shih Yin Hsiao, Wen Fang Lee, Chih Chong Wang, United Microelectronics Corporation (UMC), Taiwan


10:10 Coffee Break

S16      IGBTs

Chair:   Thomas Laska, Thomas Laska, Infineon Technologies, Germany
Co-Chair:    Jan Vobecky, ABB, Switzerland

10:30 16-1

A Novel Carrier Accumulating Structure for 1200V IGBTs Without Negative Capacitance and Decreasing Breakdown-Voltage
Md Tasbir Rahman, Keisuke Kimura, Takeshi Fukami, Yasuki Futamura, Kimimori Hamada, Toyota Motor Corporation, Japan

10:55 16-2

Study on the Improved Short-Circuit Behavior of Narrow Mesa Si-IGBTs with Emitter Connected Trenches
Katsumi Eikyu, Atsushi Sakai, Hitoshi Matsuura, Yoshito Nakazawa, Yutaka Akiyama, Yasuo Yamaguchi, Renesas Electronics Corp., Japan

11:20 16-3

An Advanced Soft Punch Through Buffer Design for Thin Wafer IGBTs Targeting Lower Losses and Higher Operating Temperatures Up to 200°C
Elizabeth Buitrago, Athanassios Mesemanolis, Charalampos Papadopoulos, Chiara Corvasce, Jan Vobecky, Munaf Rahimo, ABB Semiconductor, Switzerland

11:45 16-4

Investigation of the Mechanism of Gate Voltage Oscillation in 1.2kV IGBT Under Short Circuit Condition
Takuo Kikuchi, Kazutoshi Nakamura, Kazuto Takao, Toshiba Corporation, Japan


12:10 Lunch Break

S17      Invited Papers

Chair:   
Co-Chair:   

13:30 17-1


13:55 17-2



14:20 Coffee Break

Closing


18:30

TPC Dinner (by Invitation)